To overcome the SCEs, innovative device designs had expected. Due to such heavy SCE over nanometer regime, gate is unable to control the channel in the semiconductor(Anju, 2016). MOSFET below 22nm, several unsolicited effects are occurring like Punch through, subthreshold slope & leakage current. By minimizing the size of the planar transistor i.e. The nonstop scrambling in MOSFET length has focused to several challenges that is disappearing gate control on the channel station that marks in Short Channel Effects (SCEs) and heavy leak current. The effect on ratio of on current (ION) and off current (IOFF), threshold voltage (VTH), subthreshold slope (SS), and drain-induced barrier lowering (DIBL) is observed.ĬMOS skill is the most fundamental and talented technology in relations of sizing, speed, active power dissipation, high performance & device & circuit level working, etc. The approach and simulation of 3Dimensional Fin-FET is carried to evaluate the better performance parameters of device for change in gate length by deploying different dielectrics materials. The paper focuses on the study of geometry-based device design of Fin-FET by changing high k dielectrics materials from silicon SiO2 (3.9), Hafnium Oxide (HfO2), and metal gate work function ranging from 4.1eV to 4.5eV. The work highlights results of the current-voltage electrical characteristics of the n-channel triple gate Fin-FET gatherings. Multi-gate MOSFET generally measured as Fin-FET is the best substitute vital to stunned short channel effects. AbstractThe scrambling of MOSFET below 22nm, 14nm, unwanted Short Channel Effects (SCE) like punch through, drain-induced barrier lowering (DIBL), along with huge leakage current are flowing through the device, which is not recognized for better performance.
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